1. Field
The present disclosure relates to communication networks. More specifically, the present disclosure relates to a method and system for facilitating in-order traffic aggregation.
2. Related Art
The proliferation of the Internet and e-commerce continues to fuel evolutions in the telecom and network industries. Convergence in the underlying network architectures often takes place at a pace faster than the lifespan of most network equipment. For example, a large enterprise network today may contain Internet Protocol (IP) networks, storage area networks (SANs), Ethernet-based access networks, and leased lines and switches from telephone service providers. How to manage and fully utilize the equipment capacity in a heterogeneous environment remains an ongoing challenge.
To maximize returns on capital expenditures, many network architects prefer re-using existing equipment to switch data packets of different formats and aggregating low-speed switch ports to provision high-speed logical links. To achieve such a goal, I/O consolidation is needed. I/O consolidation is the ability to carry different types of traffic, having different traffic characteristics and handling requirements, over the same physical media.
In storage networking, Fibre Channel (FC) is the most widely used protocol, thus making FC an essential component in I/O consolidation solutions for data centers. Fibre Channel over Ethernet (FCoE) allows FC type of traffic to be transported over an Ethernet network. Hence, an Ethernet network can be used in a data center for consolidating flows from FC and Internet Protocol (IP), as well as other types of traffic. As a result, the different types of traffic can share a single, integrated infrastructure, thereby reducing network complexities in the data center.
To enable FCoE, FC frames can be encapsulated inside an Ethernet frame to allow them to be transported across the Ethernet network. In order to encapsulate/decapsulate FC frames, certain processing circuitry is needed. Sometimes, a mismatch may occur between the speed of an Ethernet link and the speed of the processing circuitry interface. To overcome such a mismatched condition, the Ethernet packet may arrive at the processing circuitry via multiple low-speed input ports. The processing circuitry processes the received packets and forwards them to corresponding FC ports. Because the Ethernet packet size can vary from 64 bytes to up to 1518 bytes, the packets received from the multiple low-speed input ports may be processed and forwarded out of order.
To re-sequence the packets, a conventional approach is to attach a packet sequence number to each Ethernet packet and place received packets into a large memory. A resequencing mechanism then re-orders the packet flow within the large memory based on the packet sequence number. Such an approach relies on a memory that is large enough to buffer many packets, such as hundreds of Ethernet packets. However, such a large-sized memory may not be available inside the processing circuitry.